[libre-riscv-dev] 180nm ASIC layout image 03jun2020

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat Jul 4 11:12:13 BST 2020


this was an attempt to add the DIV pipeline in.  DIV is 120% larger
than everything else put together, however the layout is fascinating.
there are 8 pipeline stages (8 combinatorial blocks per stage) and the
delineation between each stage is clearly present.

i am just currently experimenting with reducing the width of the
comparisons from 192 bits to 128 and this is giving only 130,000 cells
needed rather than 140,000.  this has also got the BLIF file down from
100 megabyte to "only" 48.

trial VST files are also now down to 28k (from 500k)

realistically we need to do 32-bit DIVs only (and a loop around that 4
times to do 64-bit) as this will reduce the size of DIV by a factor of


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