[libre-riscv-dev] 180nm ASIC layout image 02jun2020

Luke Kenneth Casson Leighton lkcl at lkcl.net
Fri Jul 3 00:40:14 BST 2020

On Fri, Jul 3, 2020 at 12:33 AM <whygee at f-cpu.org> wrote:
> On 2020-07-02 20:59, Luke Kenneth Casson Leighton wrote:
> > https://libre-soc.org/180nm_Oct2020/2020-07-02_19-01.png
> breathtaking !

totally cool, right? :)

looking closely at the interaction between cells (branch, trap) which
happen to use the same regfile (FAST), those are all in close
proximity and inter-mixed.

likewise, CR regfile is at the bottom right (yellow green blob), and
Logical is the "tree" blob in the bottom middle, ALU is right next to
it, and then down the whole of the left side is the INT regfile.
ShiftRot which has a huge shifter that takes up 4% of the total area
is in the middle.

it all kinda makes sense, i would just really prefer it to be
discretely laid-out blocks, and my feeling is that this is what's
going to be needed when both DIV and MUL get added, as they're just
far too large to do an arbitrary layout.


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