[libre-riscv-dev] 130nm for the hackers : finally a reality ?
cestrauss at gmail.com
Wed Jul 1 11:16:35 BST 2020
On 06/30/2020 14:18, whygee at f-cpu.org wrote:
>From the article:
> In November, they plan to order a multiproject wafer with 40 slots. They
> don’t know yet if they will have to beg and plead to get 40 designs or
> if they will have to winnow the select down from all possible
> candidates. If you are one of the 40, you’ll get about 10mm square to
> play with and wind up with somewhere around 100 to 300 chips in
> chip-scale packaging (CSP).
> There are a few stipulations. You’ll submit your design on GitHub (or
> some similar public repository), so your design is going to be open source.
An opportunity for libre-SOC?
Are there many existing libre hardware projects, at the ASIC level, to
compete for these 40 slots?
I wonder how to solder these CSP onto a PCB,
> Let us know what IC you want to design — or see someone else design — in
> the comments.
Maybe it would be appropriate to leave a comment?
Besides libre-SOC, I myself would be very interested as well in a libre
FPGA design, with an open bitstream format and libre toolchain.
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