[libre-riscv-dev] pinmux in nmigen
rishucoding at gmail.com
Mon Mar 25 16:16:59 GMT 2019
Yes, i remember the first phase. We used to specify the specification, the
pinout in a file in a tabular format.
Then, using python templates, we generated the bsv code. Then using
bluespec compiler, it automatically generated the
For this verilog RTL, we used to model the same design in python cocotb and
test the functional correctness.
To begin, I shall experiment with some of the files to get my hands back on
Can you give more insights on where nmigen will be useful?
Earlier, bluespec used to generate verilog. But, nmigen can also generate
verilog (as we are doing in CAM).
So, are you thinking to switch to nmigen and replace bsv?
On Mon, Mar 25, 2019 at 3:35 PM Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> hi rishabh,
> i've been thinking about how we could keep you occupied with a task,
> that would also allow you to become familiar with nmigen, and the most
> sensible thing i think would be a nmigen version of the pinmux.
> basically, going *right* back to the start of when we worked on the
> BSV version, that first phase which creates code that understands the
> specification, and getting it to output verilog that matches *exactly*
> that cocotb unit test we created and you worked on, remember?
> the second phase - the Interface Infrastructure Generator - we'll
> leave that for now as it's waaaaay comprehensive and very closely tied
> to the Shakti E-Class.
> what do you think?
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> libre-riscv-dev at lists.libre-riscv.org
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