[libre-riscv-dev] IEEE754 FPU turning into ALU with Reservation Stations

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat Mar 23 13:03:14 GMT 2019

okaaay i've been slowly morphing the IEEE754 FPU add code such that
every module now has a function that defines its input and output data
specification.  in two cases i was able to use a new class called
"StageChain" which, as its name states, "chains" some stages together,
through the fact that the modules (stages) all conform to the same

i've also made the decision to have the output from SpecialCases pass
all the way through.  although it is still a state-based design, the
data is *still* going down a pipeline-like arrangement, with no

all this whilst still keeping the unit tests running, so as to avoid
the nightmare situation of having to wade through some extremely
complex code to track down some obscure error.

it is *almost* at the phase where it can now be turned into an actual
pipeline.  i have yet to work out the synchronisation in and out,
basically how to replace John Dawson's ACK/BUSY with the VALID/READY

what i might do there is create a zero-length pipeline (or a
passthrough single-stage one) as a separate much simpler piece of
code, then drop the adder pipeline in place of the passthrough one.


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