[libre-riscv-dev] buffered pipeline
programmerjake at gmail.com
Fri Mar 15 00:58:33 GMT 2019
On Thu, Mar 14, 2019, 17:48 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
> On Thu, Mar 14, 2019 at 6:20 PM Jacob Lifshay <programmerjake at gmail.com>
> > If that is still too much, we can change the simple stage so it deasserts
> > input.accepting when output.accepting is deasserted even if it is empty
> > the moment. that would change the simple stage so the *.accepting signals
> > are directly connected together.
> yes, i think this would work.
I do prefer the current system since it fills bubbles in the pipeline when
a later stage stalls, increasing pipeline utilization.
> i'd also like to see what happens when
> a stage itself determines that it has to stall. for example, the
> FPDiv will have several pipeline stages that don't stall, and one that
> will loop for anything up to 50 cycles.
I'll build a few demo pipelines to show how it would work.
I could add a StallIsolatorStage that isolates the stalling behavior and is
a 0-cycle passthrough when not stalling and a single cycle delay when
stalling as previously discussed.
I'd also build a integer divider that stalls as a stalling demo, though it
might be more productive to build a simple stalling load/store unit.
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