[libre-riscv-dev] buffered pipeline

Luke Kenneth Casson Leighton lkcl at lkcl.net
Fri Mar 15 00:47:26 GMT 2019

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On Thu, Mar 14, 2019 at 6:20 PM Jacob Lifshay <programmerjake at gmail.com> wrote:

> If that is still too much, we can change the simple stage so it deasserts
> input.accepting when output.accepting is deasserted even if it is empty at
> the moment. that would change the simple stage so the *.accepting signals
> are directly connected together.

 yes, i think this would work.  i'd also like to see what happens when
a stage itself determines that it has to stall.  for example, the
FPDiv will have several pipeline stages that don't stall, and one that
will loop for anything up to 50 cycles.


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