[libre-riscv-dev] Wish to work on
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Fri Mar 8 04:32:20 GMT 2019
On Friday, March 8, 2019, Rishabh Jain <rishucoding at gmail.com> wrote:
> "yosys > read_verilog Cam.v" runs fine, console log ends with
> finished Verilog frontend".
> I get a error message when I do "yosys > show" :
> "2. Generating Graphviz representation of design.
> ERROR: For formats different than 'ps' or 'dot' only one module must be
Aah I have been hand editing the verilog file and cutting it back to
contain only one module. Search "module top"
> But, "yosys > show -format dot " this works fine: ends with "Dumping
> anonymous to page 8"
Ah great, I will try that
> Then, linking the python3.6 binary with python3 works. Now, python3
> python3.6 binary. Thanks!
> I was able to observe the waveform.
> I tried to right click on "top" (position is left top side in my case),
Yes. Same here
> not option were coming.
Hm, left click first? Signals should appear in lower part of left pane.
> Though, I was able to load all the signals by "Search -> Signal Search
> -> select 'top' and insert"
> Yes, the waveforms are pretty clean and clear.
> Yep, I have cocotb installed.
> Now, i guess the tools are working fine.
> can you share the specifications for TLB and CAM which we intend to
Still being discussed, search archives for subjects "TLB".
We really need to start using bugtracker soon, number of outstanding issues
and discussions is beyond ability to memorise.
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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