[libre-riscv-dev] rowhammer mitigation
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Tue Mar 5 19:14:37 GMT 2019
we're starting to lose track of things like this, could you put it on
the requirements page (as a bulletpoint)
really need to start using the bugtracker.
On Tue, Mar 5, 2019 at 5:48 PM Jacob Lifshay <programmerjake at gmail.com> wrote:
> when we build the memory controller, we will need to ensure that we have
> some protection against rowhammer.
> Mitigation options:
> Count row accesses and refresh adjacent rows when there are too many in a
> short time. requires both of: counters for every dram row, which would
> probably take 32kB to 48kB of sram (assuming 16k rows), and knowing the
> mapping from physical addresses to dram rows, which may be difficult to
> Increase the refresh rate (uses more power when idle).
> randomly refresh adjacent rows on every access (1 chance in 16k might work,
> have to do more research). Also requires knowing the mapping from physical
> addresses to dram rows, which may be difficult to determine. May be
> patented, have not checked (intel ivy bridge and later xeon processors
> implement this with increased refresh rate as a fallback).
> Note that most ddr3 and some ddr4 chips are vulnerable to rowhammer.
> Jacob Lifshay
> libre-riscv-dev mailing list
> libre-riscv-dev at lists.libre-riscv.org
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