[libre-riscv-dev] rowhammer mitigation
programmerjake at gmail.com
Tue Mar 5 17:48:14 GMT 2019
when we build the memory controller, we will need to ensure that we have
some protection against rowhammer.
Count row accesses and refresh adjacent rows when there are too many in a
short time. requires both of: counters for every dram row, which would
probably take 32kB to 48kB of sram (assuming 16k rows), and knowing the
mapping from physical addresses to dram rows, which may be difficult to
Increase the refresh rate (uses more power when idle).
randomly refresh adjacent rows on every access (1 chance in 16k might work,
have to do more research). Also requires knowing the mapping from physical
addresses to dram rows, which may be difficult to determine. May be
patented, have not checked (intel ivy bridge and later xeon processors
implement this with increased refresh rate as a fallback).
Note that most ddr3 and some ddr4 chips are vulnerable to rowhammer.
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