[libre-riscv-dev] berkeley-softfloat-3 implements different variants of IEEE754

Luke Kenneth Casson Leighton lkcl at lkcl.net
Fri Mar 1 19:52:41 GMT 2019

On Fri, Mar 1, 2019 at 7:12 PM James Cloos <cloos at jhcloos.com> wrote:
> >>>>> "HB" == Hendrik Boom <hendrik at topoi.pooq.com> writes:
> HB> Or is the RISC-V convention a violation of the IEEE arithmetic spec?
> It is not a violation of the spec.  Some variation was added so that
> existing hardware could be in-spec.

 arrrgh.... allowing variation is precisely and exactly what makes a
specification a failure.

> (Not just for x86, also for ibm's,
> sparc, alpha, et alia.)  They ended up with no requirements on the nan
> payloads.  Only the Q-vs-S bit is required.
> Perhaps would make sense to patch softfloat to enable run-time selection
> of such variants?

i heard from john hauser and learned that that's almost what's
possible to do: it's only possible at *compile* time.  originally it
was not obvious - at all, from the softfloat website page - that it
was even possible to select different variants.

theoretically it would be possible to compile all of the variants and
select them with a switch statement or a function lookup table: the
only problem being, (a) that costs time to do and (b) it would affect
performance, where in some cases the relevant code is actually
compiled *inline*, due to the code often being used in emulators.


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