[libre-riscv-dev] berkeley-softfloat-3 implements different variants of IEEE754
cloos at jhcloos.com
Fri Mar 1 19:11:49 GMT 2019
>>>>> "HB" == Hendrik Boom <hendrik at topoi.pooq.com> writes:
HB> Or is the RISC-V convention a violation of the IEEE arithmetic spec?
It is not a violation of the spec. Some variation was added so that
existing hardware could be in-spec. (Not just for x86, also for ibm's,
sparc, alpha, et alia.) They ended up with no requirements on the nan
payloads. Only the Q-vs-S bit is required.
Perhaps would make sense to patch softfloat to enable run-time selection
of such variants?
James Cloos <cloos at jhcloos.com> OpenPGP: 0x997A9F17ED7DAEA6
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