[libre-riscv-dev] [Bug 64] data handling / io control / data routing API needed

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Tue Apr 30 14:52:37 BST 2019


--- Comment #46 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #39)

> I don't think we should use nmigen's FIFO interface, having an interface
> like was in the original Chisel code with a separate enq (entry) and deq
> (exit) port means that Queue is a Block rather than changing Queue to fit
> nmigen's FIFO interface only to then need to adapt back to the 2-port
> interface everywhere.

 just to be absolutely clear: i changed ONLY the NAMES.  i did NOT alter

 the change in name is documented at the top of the file:

            din  = enq_data, writable  = enq_ready, we = enq_valid
            dout = deq_data, re = deq_ready, readable = deq_valid

 thus, if you are considering that Queue is a Block simply by changing
 some characters of variable names using global/search/replace substitution,
 this is clearly false.

 from this clearly being false, it is just as equally clear that Queue
 *EQUALS* block *EQUALS* FIFOControl *EQUALS* ControlBase in terms of
 their API equivalence, as far as the ready/valid/data entry and exit
 is concerned (and that, pure and simple, only the names are changed).

 Block valid/ready EQUALS FIFOInterface writable/we - readable/re.


 other parameters are added, yes - these have NOTHING TO DO WITH the plain
 and simple fact that the ready/valid/data IS EXACTLY THE SAME.

 does that make sense?

 all of these objects *really do have exactly the same fundamental API*

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