[libre-riscv-dev] [Bug 48] Complete IEEE754 floating point pipeline

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Fri Apr 26 21:51:22 BST 2019


--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #1)
> comment from jacob (to be discussed to create separate milestones):
> I think we should split this into the div/mod/sqrt/inv-sqrt pipeline
> (referred to as div pipeline hereafter) and the main pipeline. In
> particular,  I'm planning on having the div pipeline also handle integer
> div/mod and having the main pipeline handle integer multiplication and
> probably additional operations.

i just created a FMUL bugreport/milestone, which depends on the
integer-mul one, before seeing this, so we're along the same

didn't occur to me about the DIV.  DIV already exists as an FSM,
so there's no need to duplicate the work already done there.

looking at the code, now, the need to split it out does not appear
to be as urgent as it clearly is for MUL, being as DIV is, nothing
more complex than ADDs, 1-bit shifters, CMPs, XORs and SUBs.

it's just not that complicated.

MUL on the other hand, is a *massive* block of gates, and the need
to break it out behind an API that gives us the option to reduce
gate count (at the cost of increasing pipeline stage length) is
quite clear.

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-riscv-dev mailing list