[libre-riscv-dev] [Bug 72] verilog to nmigen converter (full or partial) needed

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Thu Apr 25 22:52:37 BST 2019


--- Comment #13 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
parameters sort-of done:

    input  logic                        prefetch_i,
    input  logic [AXI_S_ADDR_WIDTH-1:0] in_addr_i,
    input  logic     [AXI_ID_WIDTH-1:0] in_id_i,
    input  logic                  [7:0] in_len_i,

class fsm:
    def __init__(AXI_M_ADDR_WIDTH=40,
        self.prefetch_i = Signal() # input
        self.out_addr_i = Signal(AXI_M_ADDR_WIDTH) # input
        self.in_id_i = Signal(AXI_ID_WIDTH) # input
        self.in_len_i = Signal(8) # input

i am however wondering if the use of python AST is interfering
with the pace at which this code could be written, or whether
it could turn out to be useful.

it's actually really hard to tell if information would be lost
by choosing to drop down to ad-hoc data structures and plain

i am starting to get used to examining the c++ code (from
icarus verilog parse.y) and using it for not just guidance
but as *actual code* that works, after some form of regular
pattern-match substitution from c++ to python.

this is extremely weird to involve *three* simultaneous
languages... python, verilog, and c++ ....

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