[libre-riscv-dev] [Bug 72] New: verilog to nmigen converter (full or partial) needed

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Mon Apr 22 17:29:14 BST 2019


            Bug ID: 72
           Summary: verilog to nmigen converter (full or partial) needed
           Product: Libre Shakti M-Class
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

a *lot* of verilog code is being manually converted to nmigen,
it's getting boring.  time to write a tool that helps.  simplest
one initially is just a straight string/pattern-matcher...
more sophisticated (later) can use python-ply and find a BNF
lex/yacc format for it [python-ply can auto-convert c-style
lex/yacc BNF into a stub python module]

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