[libre-riscv-dev] TLB

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sun Apr 21 23:32:17 BST 2019


Daniel this looks familiar, I can see parallels with what you begun. The
FSM responds to bits instead of "COMMAND", I can see some things related to
both L1 and L2.

The code is heavily integrated with AXI4 Lite, which makes sense in that
AXI4 divides into control and data channels.

That it is software configureable (memory-addressable registers) makes it
quite attractive.

Basically on AXI4 you specify an area of memory that, if read or written is
some config registers, and another area on the same channel will be the
main data area.

Whether that data area is actually memory, or a cache, or a peripheral, is
entirely up to you.  AXI4 doesn't care! It just responds to reads and

The only thing with this code, the search algorithm for the L2 TLB is quite
poor, it is linear, and a FSM.

I start to see why you asked about the PLRU, it would be possible to use
the same PLRU module from ariane ptw in the L2 Cache.

A software configureable MMU is really attractive, it allows protection of
IO devices. Been looking for this for a year, this is the first one I have

Hooray :)

crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

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