[libre-riscv-dev] [Bug 70] evaluate Bus Architectures

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=70

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
* https://github.com/peteut/migen-axi
* https://github.com/Nic30/hwtLib/tree/master/hwtLib/amba - would require a
hwtLib nmigen back-end (or use the verilog back-end)

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