lkcl at libre-riscv.org
Sat Apr 20 21:56:35 BST 2019
On Sat, Apr 20, 2019 at 9:40 PM Daniel Benusovich
<flyingmonkeys1996 at gmail.com> wrote:
> > > Are we using the ariane TLB instead now since it is working?
> > honestly, use ariane one! it works... therefore... makes sense and saves time!
> Alrighty then. Should the two level caching be added in as well as the
> Cam and assoc cache?
honestly, i was thinking of following ariane, converting mmu.sv next,
so modifying the ariane ptw.py or tlb.py too much would lead to
(btw, mmu.sv is dead simple: it instantiates a couple of tlbs, and a
couple of ptws, and... er.... links them together).
however... hmmm, ariane doesn't appear to have any evidence in the
code of *having* an L2 cache!
so i am not sure what to suggest.... although... logically... i
*think*... if we have like... a Wishbone Bus, where the memory access
go through that before getting to the actual physical memory, then L2
is like, completely separate.
so can we focus on AssocCache, TLB and PTW initially?
and, shall i do mmu.sv converted to nmigen? do you want to take a
look first, see what you think:
it really does just (mostly) link instruction/data tlbs and ptws together.
> > also, can you see if you can work out some better unit tests for
> > ariane tlb.py, then, the next stage, adapt it to use PteEntry and so
> > on?
> > but, *only* do the adaptation once the unit tests for ariane tlb.py
> > are functional, because any mistakes in the adaptation will show up.
> Sounds good unit tests then adding in the CAM, assoc cache, and other modules.
> > AssocCam going ok?
> I need to pull out the PLRU module from the TLB.
that's a good idea, split out into plru.py, perhaps even tlbcontent.py as well
> It would be much
> nicer to use that instead of remaking one. After that it should be
> easy pickings one I figure out how it works and integrate it in.
ack, hopefully yes.
oh! btw, i got the order of the ports in class PTE wrong! this
results in the order of the bits coming out of PTE.flatten in the
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