[libre-riscv-dev] [Bug 65] New: variable-length in / variable-length out queue needed

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Fri Apr 19 09:16:05 BST 2019


            Bug ID: 65
           Summary: variable-length in / variable-length out queue needed
           Product: Libre Shakti M-Class
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

in many scenarios, data comes in at a different speed or bitrate from
the speed or bitwidth at which it goes out.  examples:

* UART handling.  data comes in bit-wise, goes out byte-wise
* Wishbone / AXI4 bridges: data comes in 64-bit, goes out 16-bit
* instruction buffer: data comes in on cache-line width, goes out 16/32/48/64

this latter is more complex in that the data needs to be inspected
intrusively in order to ascertain how much will go out.

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