[libre-riscv-dev] [Bug 60] 3-stage 64-bit multiplier pipeline needed (signed/unsigned)

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Mon Apr 15 10:36:57 BST 2019


--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
the shakti group i know did the 64-bit multiply with a series of 8-bit
multipliers, then added up the intermediate results.  mitch alsup mentioned
on comp.arch that there is a modern algorithm for extremely efficient
integer-multiply, where we should i feel assume that below a certain
granularity that we have access to such.  not least, for FPGA demos,
FPGAs have DSP blocks.

in the IEEE754 FPU code it is extremely easy to instantiate extra units,
and creating a SIMD pipeline will be a very very straightforward matter
of declaring an array of pipelines, and using Cat() to split the incoming
data and push it to the associated unit then reassemble on exit.  some
synchronisation will be required (if we allow early-out), however that
would not be difficult to achieve.

so the primary need then will be flexibility (parameterisation) on a
single block (as opposed to designing a parallel/SIMD engine): being
able to specify the two key parameters of that single block, namely:

* the required pipeline depth
* the bit-width

i say that because if a third parameter is provided (amount of parallelism)
it may actually become inconvenient to deploy in the IEEE754 FPU, as the
parallelism would be achieved at a level way above the actual integer
multiplier component.

for an integer-based ALU, on the other hand, that *will* need parallelism,
however i feel that such a "parallelising" or "array" capability is still
a separate task, needed for many many other purposes i.e. SIMD-ifiying in
general, for ADD, SHIFT, FMAC... everything in fact :)

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-riscv-dev mailing list