[libre-riscv-dev] TLB Replacement Policy
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sun Apr 14 18:23:29 BST 2019
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Sat, Feb 16, 2019 at 11:05 PM Jacob Lifshay <programmerjake at gmail.com> wrote:
> What I was thinking of is that the software handling a TLB miss would
> choose what entry to replace in the L2 TLB. For the L1, you could pick
> random or LRU. You could use a lfsr for the random number generator. we
> would need a way to save and restore the lfsr state to avoid side-channels
> for security. for a 8-16 entry L1, an 8-bit lfsr is probably good enough.
> Using lru requires more hw to keep track, so random may be better.
i decided to have a go at converting the ariane tlb and ptw verilog to
nmigen, and it looks really clean, and reasonably straightforward and
therefore easy to understand.
the pseudo-lru algorithm that the team behind ariane came up with was
to transform the LRU into a bit-tree.
could people take a look and see what you think?
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