[libre-riscv-dev] pipeline sync issues

Jacob Lifshay programmerjake at gmail.com
Fri Apr 12 08:37:55 BST 2019

On Thu, Apr 11, 2019 at 11:43 PM Luke Kenneth Casson Leighton <lkcl at lkcl.net>

> the advantage of this approach is that if it's determined that there
> is too great a gate delay, all that's needed is: split those
> daisy-chains into shorter ones, throw the shorter bits at another
> derivative of ControlBase, and the overall pipeline goes up by one
> cycle...
> .... *with very little coding effort*.
> unfortunately, it's not quite that simple (that's what pipeline.py is
> supposed to be for), it's necessary to determine and change the
> ispec/ospec, as part of any given (hypothetical) split /
> extension-to-overall-pipeline-length.
> pipeline.py is supposed to hide even that, transparently, by
> dynamically working out the ospec and ispec depending on the runtime
> connections.
In the original code I had written, with the addition of a *Chain class,
that could have been done quite simply by adding a new instance of RegStage
in the middle of the chain (basically just calling a constructor). no other
code needs to be changed.

> > In my proposal, I'm thinking of switching the Stage/Pipeline naming to a
> > new naming scheme, to avoid confusion coming from semantics already
> > attached to those names.
>  yes.  i started switching to "Control Handling" and "Data Processing"
> a few days ago.  i left in the name "Stage" unfortunately.
Ok. Since my proposal doesn't have the same control vs. data split, I'll
probably use "block" as it has no conflicting meanings in the context of

 it had occurred to me that there may be time-related [unnecessary]
> delays associated with BreakReadyChainStage which mean that it works
> yet is sub-obtimal.  dan gisselquist warned of this as possibility
> that is common in many efforts to design valid/ready (WE/WRITEABLE +
> RE/READABLE) pipeline signalling.
Ok. BreakReadyChainStage is designed to be used sparingly, most simple
pipelines would be made from RegStage and CombStage. If we chose a variant
of RegStage that doesn't fill empty slots in a pipeline when later slots
are stalled, then ready is wired directly from input to output in both the
RegStage variant and CombStage.


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