[libre-riscv-dev] pipeline sync issues
programmerjake at gmail.com
Fri Apr 12 04:06:49 BST 2019
On Thu, Apr 11, 2019, 19:49 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> On Fri, Apr 12, 2019 at 3:03 AM Jacob Lifshay <programmerjake at gmail.com>
> > > was this what you have been referring to, jacob?
> > >
> > yeah, that's part of it.
> ok. the implications are, to be able to follow through on that: no
> Stage may contain sync. at all. anything that is chained together
> (in the intended single-cycle fashion) must be pure combinatorial.
> there must not be, under any circumstances, the use sync in the data
> path, data chaining, valid/ready or valid/ready chaining.
I don't understand how you came to that conclusion.
What I think will work best is to just not support adding additional data
signals to Stage interfaces, and then a FIFO can just be another stage with
ready/valid signalling, just like RegStage and BreakReadyChainStage. I'm
quite sure that ready/valid signalling can emulate with no additional
circuitry all of Global CE, Traveling CE, strobe/busy, and the other
pipeline control schemes except maybe for the strobe/ack scheme that
requires 2 cycles for every data element (which can be emulated by using
some adaptors). I'm writing in my new proposal how restricted cases of
ready/valid are logically identical to the other schemes.
I think that the FIFO class may be designed for crossing clock domains and
therefore has extra delay for synchronization.
More information about the libre-riscv-dev