[libre-riscv-dev] pipeline sync issues
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Fri Apr 12 02:59:32 BST 2019
On Fri, Apr 12, 2019 at 2:24 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
> FIFOControl has been tested with a simple Signal(16) as input and
> output, i'm just about to try chaining the above with a FIFOControl
> that takes the Example2OpRecord as input and output.
ok so that introduces 2 clock cycles, where one is all that's
necessary. the FIFOControl introduces a clock cycle delay, and so
does the adder (using SimpleHandshake).
if it were possible to allow FIFOControl to perform *processing* of
its input data (pre and/or post), there's no need for separate
pipe-stages, and, crucially, BufferedHandshake can be deleted.
if on the other hand the Stage API *was* the Pipe API - i.e. if
Stages contained *BOTH* data control *AND* data processing, then
hypothetically it would be possible to use combinatorial chaining
between FIFOControl and SimpleHandshake to eliminate the extra clock
was this what you have been referring to, jacob?
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