[libre-riscv-dev] pipeline sync issues

Luke Kenneth Casson Leighton lkcl at lkcl.net
Thu Apr 11 17:09:00 BST 2019

ok i think i have a draft "flattening" function that recursively
leaf-node-concatenates all Signals of a compound structure together,
and then uses Cat(*res) to produce a "flat" version of the structure.

i also worked out that overriding __setattr__ for the (new)
RecordObject needs to update the Layout, however the concerns earlier
are moot because if the field being added to the RecordObject is also
a RecordObject, it will contain a Layout object, duh.

then, with the new flatten() function, it's possible to use that for
the incoming *and* outgoing data in FIFOtest.  yes, outgoing as well,
because it's possible to assign to a Cat object:

s = Signal(32)
t = Signal(32)
u = Signal(64)


so if RecordObject gives the Cat of all its sub-objects, then flatten
on the ispec can be done on the FIFO din, and flatten on the pipe's
*outgoing* data can be assigned to equal the FIFO dout... and it's

holy cow.

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