[libre-riscv-dev] barrel processor as I/O and DMA controller

Jacob Lifshay programmerjake at gmail.com
Wed Apr 10 18:40:59 BST 2019

If we need, I do have some designs in mind for a PLL that doesn't need any
special parts other than capacitors (no op-amps, specially matched
transistors, or resistors), but they wouldn't have particularly good jitter
or anything. I'm not sure how we would put analog circuits on the SoC in
terms of HDLs. Maybe Verilog-AMS?

On Wed, Apr 10, 2019, 10:32 Luke Kenneth Casson Leighton <lkcl at lkcl.net>

> On Wed, Apr 10, 2019 at 6:30 PM Jacob Lifshay <programmerjake at gmail.com>
> wrote:
> >
> > Note that I don't think it would be particularly low power at 1GHz, so we
> > will want to run it at a lower clock rate most of the time.
>  yehyeh.  a PLL will help with that.  analog block.  must find a way
> to make that happen.
> l.
> _______________________________________________
> libre-riscv-dev mailing list
> libre-riscv-dev at lists.libre-riscv.org
> http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev

More information about the libre-riscv-dev mailing list