[libre-riscv-dev] kestrel kcp53000 developer making a nmigen RISC-V core

Luke Kenneth Casson Leighton lkcl at lkcl.net
Wed Apr 10 05:15:11 BST 2019

On Wed, Apr 10, 2019 at 4:20 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
> I spent a little time to look through this, I'll look more later.

 cool.  i'm in touch with samuel, the developer: he's going to write a
nmigen front-end for the PLU (FSM) engine that he created, allowing
him to *auto-generate* the majority of the CPU from this existing
(proven) file:

that program auto-generated the following verilog (and will
auto-generate a nmigen version soon):

 the PLU-style FSM he based on studies of how the 6502 works.  i could
have the acronym wrong....

it's an amazing approach, that only a software engineer would come up
with when faced with the challenge of designing a processor :)


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