[libre-riscv-dev] pipeline sync issues

Jacob Lifshay programmerjake at gmail.com
Tue Apr 9 07:57:03 BST 2019

continuing from a private discussion:

> i found
> out why UnbufferedPipeline (was BreakReadyChainStage) and the
> (newly-added) PassThroughHandshake (was RegStage) won't work: they all
> have loops that make their p_o_valid be set *not* on the clock cycle,
> instead ever so slightly off it.
> BufferedPIpeline (now renamed to SimpleHandshake) and BufferedPipeline
> (now renamed to BufferedHandshake) both have the condition that the
> data and its associated ready signal are latched together and use
> sync.

The way I had designed them is that all signals only need to have the
correct values at the clock edge. The signals change right after the clock
edge because they are connected to the output of flip-flops and the clock
edge is what makes the flip-flop outputs change state. the reason they
don't change exactly at the clock edge is because the signals have to first
propagate through combinatorial logic between the flip-flop outputs and the
actual signals that you were watching. This happens on the order of 100ps
(in the simulation).

Also, some of the test code I wrote changes test input signal states a
small fraction of a clock cycle after a clock edge because I have the test
process delay a little bit right after the clock edge in order to be able
to read the circuit's outputs after sufficient time had elapsed for all the
combinatorial circuits to propagate the correct signal levels from the
output of the flip-flops. if there are signals that are produced
combinatorially from the circuit's inputs then they will change shortly
after the circuit's inputs change. This happens on the order of 10-100ns
since the clock in the simulation runs at 1MHz.

In both of those cases, the circuit is functioning correctly as designed,
since the signal changes are a direct result of the clock edge, rather than
something else just taking too long, so we won't have to worry about setup
and hold time violations at this stage in the design process (the
synthesizer can (most likely) do most of those timing calculations for us

In the target CMOS process, propagation delays will be on the order of

Jacob Lifshay

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