[libre-riscv-dev] TLB key for CAM

Luke Kenneth Casson Leighton lkcl at lkcl.net
Mon Apr 8 04:20:58 BST 2019

hi daniel,

i saw you added the SetAssociativeCache code last week, it looks really good.

you probably saw, i did a tidy-up on TLB, by adding a nmigen.main,
running it, and catching some syntax errors.  where i couldn't
identify what to do, i added "XXX TODO" into the code as a comment.

one nice thing about using python, it's possible to use python
functions to split code up, reduce the indentation level
significantly, and give the function a meaningful name.  that's what i
did in TLB.py, i split search and write_L1 into their own functions.

also, could you check: i believe nmigen will set a signal to the
"default (reset)" value if it is not explicitly set, and that the
default is "0" (zero).

so... what that would mean, in turn, is, that *all* of the code which
explicitly sets signals to zero is not necessary (see below).

of course, that *assumes* that, for example, that "cam_L1.enable" does
actually default to zero!

what do you think, better to leave the resets in explicitly, so that
it's clearer what's going on?


diff --git a/TLB/src/TLB.py b/TLB/src/TLB.py
index 3538bdc..13cdb6f 100644
--- a/TLB/src/TLB.py
+++ b/TLB/src/TLB.py
@@ -54,8 +54,6 @@ class TLB():
         """ searches the TLB
         m.d.comb += [
-            write_L1.en.eq(0),
-            self.cam_L1.write_enable.eq(0),
         # Match found in L1 CAM
@@ -92,17 +90,6 @@ class TLB():
                 m.d.comb += [
-            with m.Else():
-                m.d.comb += [
-                    self.pte_out.eq(0)
-                ]
-        # Miss Logic
-        with m.Else():
-            m.d.comb += [
-                self.hit.eq(0),
-                self.perm_valid.eq(0),
-                self.pte_out.eq(0)
-            ]

     def write_l1(self, m, read_L1, write_L1):
         """ writes to the L1 cache
@@ -152,15 +139,6 @@ class TLB():
                 # TODO
                 #with m.Case("11"):

-        # When disabled
-        with m.Else():
-            m.d.comb += [
-                self.cam_L1.enable.eq(0),
-                # XXX TODO - self.reg_file.enable.eq(0),
-                self.hit.eq(0),
-                self.perm_valid.eq(0), # XXX TODO, check this
-                self.pte_out.eq(0)
-            ]
         return m

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