[libre-riscv-dev] pipeline stages controlling delays

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sun Apr 7 01:12:13 BST 2019

On Sat, Apr 6, 2019 at 9:06 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:

> > (makes me wish we were using Rust:
> > CombStage would just be:
> > impl<I: SignalGroup, O: SignalGroup, F: Fn(I, &mut Module) -> O> Stage<I,
> > O> for F {...}
>  it's probably doable, using iterators and reduce, or something
> equally obscure.  overriding __add__ or something as a way to connect
> two stage instances [basically __add__ is calling connect_to_next,
> then reduce on... you get the idea]
>  actually... *click*... the input "type" and the return "type" of the
> function: that's it.  it should be possible to do introspection on
> them.

 i recorded this here as a low-priority enhancement, so that it's not lost:

 we need to pick some names for the repo and the python top-level name.

 also was it clear about the reasons for the separation? the data
controller handles "how" and the data "producer" creates the "what",
and combining the two results in confusion and cross-contamination of
roles.  it's a sort-of application of the Model-View-Controller


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