[libre-riscv-dev] IEEE754 FPU turning into ALU with Reservation Stations
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Thu Apr 4 08:38:37 BST 2019
On Thu, Apr 4, 2019 at 7:02 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
> On Thu, Apr 4, 2019 at 6:40 AM Aleksandar Kostovic
> <alexandar.kostovic at gmail.com> wrote:
> > okay, so that was funny. turns out I didn't exactly understand what to do,
> > despite looking and the pipeline_example.py file. Will wait to see how you
> > do get_a stage so I can do put_z similarly.
> that's because i'm getting it all hopelessly wrong and making a mess, myself :)
ok i think i have a strategy. the idea is, to *return* things from
the various functions (as a list if there are 2 or more of them), and
to use singlepipe's eq() function to m.d.sync them to a corresponding
list of items that they need to be assigned to.
if the "thing" being returned is a compound object, use an ObjectProxy
(see new decode2 fn), otherwise just make a Signal
first though modify fmul.py to use the new get_op() syntax, i'll do fdiv.py ok?
More information about the libre-riscv-dev