[libre-riscv-dev] IEEE754 FPU turning into ALU with Reservation Stations
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Thu Apr 4 06:08:23 BST 2019
ok aleksander, you want to help morphing the fpmul.py code a little so
that it starts to look like PipelineStageObjectExample in
where all the functions are being used, e.g. get_op and de_normalised
etc., all of those now need to *return* their arguments, instead of
performing an m.d.sync *inside* the function.
the next phase will be: the m.d.syncs can then be replaced (all of
them) with assignments in each "with State" block, later, where
__setattr__ will over-ride (catch) the assignment and carry out the
however, all of the m.d.syncs need to be extracted to *outside* of the
if i start at the top (get_op), you start at the bottom (put_z)? i'll
work out how to transform get_op ok?
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