[libre-riscv-dev] IEEE754 FPU turning into ALU with Reservation Stations

[Luke Kenneth Casson Leighton]

ok aleksander, you want to help morphing the fpmul.py code a little so
that it starts to look like PipelineStageObjectExample in
pipeline_example.py?

where all the functions are being used, e.g. get_op and de_normalised
etc., all of those now need to *return* their arguments, instead of
performing an m.d.sync *inside* the function.

the next phase will be: the m.d.syncs can then be replaced (all of
them) with assignments in each "with State" block, later, where
__setattr__ will over-ride (catch) the assignment and carry out the
m.d.sync *automatically*.

however, all of the m.d.syncs need to be extracted to *outside* of the
functions, first.

if i start at the top (get_op), you start at the bottom (put_z)?  i'll
work out how to transform get_op ok?

l.