[libre-riscv-dev] GPU design

lkcl lkcl at libre-riscv.org
Wed Dec 5 11:38:21 GMT 2018

On Wed, Dec 5, 2018 at 10:00 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
> On Wed, Dec 5, 2018, 01:33 lkcl <lkcl at libre-riscv.org wrote:
> > On Wed, Dec 5, 2018 at 9:23 AM Jacob Lifshay <programmerjake at gmail.com>
> > wrote:
> > >
> > > having a scoreboard doesn't mean you have to have imprecise exceptions,
> > you
> > > could have a scoreboard + reorder buffer,
> >
> >  ahh ok.  hm let me think that one through.
> >
> > on first impressions, i _think_ it basically means that it's the same
> > as the tomasulo+rob, except with the reservation stations removed, the
> > scoreboard is now the central bottleneck _and_ there is one extra
> > clock cycle (at least) where results which formerly went directly from
> > outputs over the CDB into multiple locations must now go to the
> > register file...
> >
> Forwarding can be added, so as to eliminate the 1 cycle delay.


 ... where forwarding is basically an inherent built-in design feature
of the tomasulo algorithm.  as in, *only* forwarding is possible [via
the CDB bus].  the only way that forwarding would not occur is if the
result was written back to the destination before another instruction
needed that register as a src.

 this is really the thing i'm not liking about scoreboarding: if you
want to deal with exceptions, you have to add it *on top* of
scoreboarding.  if you want to deal with stalls, you have to add
register renaming *on top* of scoreboarding.  and so on and so forth.

 it's still not clear how to get a multi-issue version, and it's still
necessary to work out how to augment it to do SV.


 ... nope.  it's just not making any sense to me.  it describes the
*effects* ("decode stage checks for hazards") without actually saying
what those hazards are, or, crucially, *how* they're checked.


slightly better - yet sufficiently obtuse to be unintelligable.

i think really i need a diagram.... huh, that's interesting:

slide 11.

> >
> >  ... or, not the register file but the register _rename_file, instead.
> >
> > in other words the reg-rename file is very similar to the reservation
> > stations.
> >
> The reg-rename file is only referenced at decode time, the rest of the cpu
> only sees the new register names.

 i need to find a diagram.

> >
> > > or you could have the scoreboard
> > > not execute instructions until all prior instructions are known to not
> > trap.
> >
> >  which means having to assess them all and special-case them.  LD/ST
> > being the main ones.
> >
> Most of them don't trap, so that wouldn't be too hard. In particular, none
> of the fp arithmetic instructions trap.

 yes.  RV, you check a flag, to find out afterwards if the result was ok.  whew.


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