[libre-riscv-dev] GPU design

Jacob Lifshay programmerjake at gmail.com
Wed Dec 5 09:59:44 GMT 2018

On Wed, Dec 5, 2018, 01:33 lkcl <lkcl at libre-riscv.org wrote:

> On Wed, Dec 5, 2018 at 9:23 AM Jacob Lifshay <programmerjake at gmail.com>
> wrote:
> >
> > having a scoreboard doesn't mean you have to have imprecise exceptions,
> you
> > could have a scoreboard + reorder buffer,
>  ahh ok.  hm let me think that one through.
> on first impressions, i _think_ it basically means that it's the same
> as the tomasulo+rob, except with the reservation stations removed, the
> scoreboard is now the central bottleneck _and_ there is one extra
> clock cycle (at least) where results which formerly went directly from
> outputs over the CDB into multiple locations must now go to the
> register file...
Forwarding can be added, so as to eliminate the 1 cycle delay.

>  ... or, not the register file but the register _rename_file, instead.
> in other words the reg-rename file is very similar to the reservation
> stations.

The reg-rename file is only referenced at decode time, the rest of the cpu
only sees the new register names.

> > or you could have the scoreboard
> > not execute instructions until all prior instructions are known to not
> trap.
>  which means having to assess them all and special-case them.  LD/ST
> being the main ones.
Most of them don't trap, so that wouldn't be too hard. In particular, none
of the fp arithmetic instructions trap.

> > If we ended up with imprecise exceptions, I'd be very tempted to just
> build
> > a barrel processor instead.
>  yehyeh.  well, let's keep exploring.
> l.
> _______________________________________________
> libre-riscv-dev mailing list
> libre-riscv-dev at lists.libre-riscv.org
> http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev

More information about the libre-riscv-dev mailing list