[Libre-soc-sim] Progress

[Peter Hsu]

Hi Luke, All,

I migrated the fast interpretation code from the old Caveat to Uspike.  
Now by default uspike uses spike instruction semantics, but you can 
override it with "fast" code:

   "c.andi"     : { "fast":"wrd(r1 & immed)" },
   "c.subw"    : { "fast":"wrd(int32_t(r1) - int32_t(r2))" },
   "c.addw"    : { "fast":"wrd(int32_t(r1) + int32_t(r2))" },
   "c.j"           : { "fast":"wpc(pc+immed); break" },

Spike laboriously extract register fields and construct immediate values 
every time, but fast code uses predecoded instructions. Only compressed 
and standard integer instructions have fast code. The result is 
approximately 2x speedup:

peterhsu at DELL-LAPTOP:~/TRY$ uspike cc1 cccp.i
rt_sigaction called
rt_sigaction called
   1000000000 insns 5.1s 196.8 MIPS record_control_macro import_hash 
lookup_import add_import check_precompiled check

...

time in parse: 0.860441
time in integration: 0.055209
time in jump: 0.500217
...
   2636831625 insns 13.6s 194.5 MIPS

Cheers,

Peter


On 14/8/21 22:28, lkcl wrote:
>
> On August 14, 2021 7:11:28 PM UTC, Peter Hsu <peter.hsu at bsc.es> wrote:
>> If anyone interested in POWER port let me know, I am happy to help.
> appreciated.  may take a couple of months before we hear about the NLnet Grant to cover it.
>
> in the meantime there is some (weekend, part-time) work to put pieces in place.  Power ISA decoding is a lot more comprehensive (a bit of a mess), over 30 "Forms" (RV is i think only seven) fortunately for INT/FP registers the fields are in the same place.
>
> in theory given that we have everything in machine-readable files (pseudocode, instruction forms) it _should_ be a relatively straightforward task to generate cavatools input files.
>
> l.