[Libre-soc-sim] Progress

[Peter Hsu]

The numbers are correct--I divide #instructions by getimeofday() which 
is real time.

This is the slow version using all Spike code with softfloat; previously 
I could get 200+ MIPS using predecoded instructions.

But QEMU is even faster--I think over 1 billion instructions/second, 2-3 
x86 instructions per target instruction. However it is rather difficult 
to connect QEMU to a pipeline timing simulator, and the speed will be 
limited by timing simulator.

I expect my timing simulator modeling simple in-order pipeline to be 
around 100 MIPS (using predecoded instructions in uspike).

-Peter

p.s.  you can see interesting demonstration of thermal throttling of 
Intel processor--if I ask for frequent status (--report=1) it shows the 
speed starting at 150 MIPS and drops to 100 over several seconds.


On 13/8/21 11:54, lkcl wrote:
> On Fri, Aug 13, 2021 at 8:28 AM Peter Hsu <peter.hsu at bsc.es> wrote:
>> Hello Luke, All,
>>
>> Uspike correctly ran cc1 of Spec CPU2000 gcc (2.6 billion):
>>
>> peterhsu at DELL-LAPTOP:~/TRY/gcc$ uspike cc1 cccp.i
>> rt_sigaction called
>> rt_sigaction called
>>     1000000000 instructions in 9.032 for 110.7 MIPS record_control_macro
> am i reading that correctly, 110 million instructions per second?
> or is that part of the...
>
>> peterhsu at DELL-LAPTOP:~/TRY$ time uspike ~/rvbin/xhpcg-ref
>> 276854550706 instructions in 3110.423 for 89.0 MIPS
>>
>> real    51m50,457s
> ... 276e9 divided by 51 divided by 60... is 90 million.
>
> seriously? 90 *million* instructions per second?  but that's around 30 real
> clock cycles per simulated instruction, which is stunning.
>
> l.