[Libre-soc-isa] [Bug 1242] SV REMAP: store REMAP indices in 4 groups of 16 64-bit SPRs (or registers)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1242

--- Comment #6 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #5)
> also to consider is how to reduce the amount of context switch latency.
> a length encoding would do the trick, stored in the 128th register,
> given that VL goes from 0 to 127.

that's a good idea, except that it needs to *not* be the 128th register, since
we need to plan ahead for when we'll have more than 127 as the max length. so,
it could work to put the length in register -1, and just use registers 0-126 as
indexes...that's equivalent to putting the length in register 0 and having
register i + 1 be for element number i.

also, my idea for when we have to support indexes >=256 is we just add another
bank of registers called idxhi or something that stores the msb 8 bits for
every element and the old idx registers store the lsb 8 bits.

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