[Libre-soc-isa] [Bug 1242] SV REMAP: store REMAP indices in 4 groups of 16 64-bit SPRs (or registers)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1242

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #1)

> if there's separate registers, 

there are other reasons for doing a separate register file
that are high priority. one of them being the sheer number
of SPRs. the indices need "association" with an SVSHAPE,
and there are 4 SVSHAPEs. that in turn means QTY 128 indices,
QTY 4of. that's a whopping *512* bytes just for Indices in
a single regfile.

divided by 8 (bytes) that's 64 x 64-bit which is an alarming
64 SPRs, which is just not happening.

deep breath this in turn means adding mtidx and mfidx as two new
scalar instructions.

also to consider is how to reduce the amount of context switch latency.
a length encoding would do the trick, stored in the 128th register,
given that VL goes from 0 to 127.

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