[Libre-soc-isa] [Bug 1161] EXTRA2/3 algorithm likely inconsistent with EXTRA2 tables causing PowerDecoder2 and insndb to disagree on scalar EXTRA2 register encoding for >=r32

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1161

--- Comment #16 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #15)
> https://libre-soc.org/openpower/sv/svp64/
> https://libre-soc.org/openpower/sv/svp64/appendix

ok, I changed both the INT/FP and CR EXTRA2 algorithms:

https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=7a232bcca2fafd3696ab01598ec9aac42d7db825

I reverted all recent changes to power_svp64_extra.py and made minimal changes
that make tests pass and match the wiki commit above:

https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=3a7959910dd014c68427bb80b58bbd5e09e4d9e8

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