[Libre-soc-isa] [Bug 1161] EXTRA2/3 algorithm likely inconsistent with EXTRA2 tables causing PowerDecoder2 and insndb to disagree on scalar EXTRA2 register encoding for >=r32

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1161

--- Comment #15 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
sorry been too long since i looked at this.  i thought it was a
variable named "extra" not "spec".

original:

    if extra3_mode:
        spec = EXTRA3
    else:
        spec = EXTRA2<<1 | 0b0
    if spec[0]:
       # vector constructs "BA[0:2] spec[1:2] 00 BA[3:4]"
       return ((BA >> 2)<<6) | # hi 3 bits shifted up
              (spec[1:2]<<4) | # to make room for these
              (BA & 0b11)      # CR_bit on the end
    else:
       # scalar constructs "00 spec[1:2] BA[0:4]"
       return (spec[1:2] << 5) | BA

insert correction here:

    if extra3_mode:
        spec = EXTRA3
=>> elif  <===
    else:
        spec = EXTRA2<<1 | 0b0

two pages,

https://libre-soc.org/openpower/sv/svp64/
https://libre-soc.org/openpower/sv/svp64/appendix


i need you to keep diffs to the absolute minimum.

https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=a723e3c7726241dc2b505b66a43932b841696dbc

please revert ALL changes that you made, in the branch (do not worry
about tests failing), start again including on PowerDecoder2,
and make ONLY changes that keep
to the absolute bare minimum of CLEAR diff changes.

that way i can easily review them.

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