[Libre-soc-isa] [Bug 1161] EXTRA2/3 algorithm likely inconsistent with EXTRA2 tables causing PowerDecoder2 and insndb to disagree on scalar EXTRA2 register encoding for >=r32

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Tue Sep 19 21:29:17 BST 2023


https://bugs.libre-soc.org/show_bug.cgi?id=1161

--- Comment #11 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #9)
> (In reply to Luke Kenneth Casson Leighton from comment #5)
> > the use of the intermediate variable "extra" is there to make the
> > spec easier to read. please preserve it. use the following strategy:
> 
> ok, I'm assuming you mean `spec`.

no i said the extra variable, as it was before you made changes

> I changed the code to:
> ```
>     if extra3_mode:  # EXTRA3 scalar is EEnnnnn vector is nnnnnEE
>         spec = EXTRA3

extra =

>     elif EXTRA2[0]:  # EXTRA2 vector gives r0-126 in steps of 2 nnnnnE0
>         spec = EXTRA2 || 0b0

extra =

>     else:            # EXTRA2 scalar gives range r0-r63 0Ennnnn
>         spec = EXTRA2[0] || 0b0 || EXTRA2[1]

-- 
You are receiving this mail because:
You are on the CC list for the bug.


More information about the Libre-SOC-ISA mailing list