[Libre-soc-isa] [Bug 1161] EXTRA2/3 algorithm likely inconsistent with EXTRA2 tables causing PowerDecoder2 and insndb to disagree on scalar EXTRA2 register encoding for >=r32

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1161

--- Comment #9 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #5)
> the use of the intermediate variable "extra" is there to make the
> spec easier to read. please preserve it. use the following strategy:

ok, I'm assuming you mean `spec`.

I changed the code to:
```
    if extra3_mode:  # EXTRA3 scalar is EEnnnnn vector is nnnnnEE
        spec = EXTRA3
    elif EXTRA2[0]:  # EXTRA2 vector gives r0-126 in steps of 2 nnnnnE0
        spec = EXTRA2 || 0b0
    else:            # EXTRA2 scalar gives range r0-r63 0Ennnnn
        spec = EXTRA2[0] || 0b0 || EXTRA2[1]
    if spec[0]: # vector
        return RA || spec[1:2]
    else:       # scalar
        return spec[1:2] || RA
```

what do you think? I'll update the rest after getting your ok.

https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/svp64.mdwn;h=f5b9e9ef340a6861630deb8848ac5ef72f6793fc;hb=ac4a9288f342e451fa4dbcab7db3321e8a14d9c7#l1192

now that I'm looking a bit more, I think we should use the syntax used by
PowerISA's pseudocode, so it needs a bit more adjustment.

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