[Libre-soc-isa] [Bug 1092] OPF RFC ISA WG questions feedback on ls002 float-load-immediate

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Wed May 31 23:36:40 BST 2023


--- Comment #8 from Paul Mackerras <paulus at ozlabs.org> ---
(In reply to Jacob Lifshay from comment #7)
> (In reply to Paul Mackerras from comment #3)
> > Has thought been given about what fishmv should do in exception conditions?
> > What if FRS contains a Signalling NaN initially? Should fishmv generate a
> > VXSNAN exception in that case? Or do you consider this to be a move-type
> > instruction (like fmr) which never generates exceptions?
> this is a move-type instruction therefore never generates exceptions. this
> is specifically necessary because otherwise fmvis/fishmv wouldn't be able to
> encode all possible f32 sNaNs and end up with the exact same sNaN in the
> register.
> fmvis/fishmv is intended as a replacement for doing a f32 load from a
> constant, so being able to express sNaNs is necessary

Sounds reasonable. An explicit statement about that in the instruction
description would be useful.

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