[Libre-soc-isa] [Bug 1092] OPF RFC ISA WG questions feedback on ls002 float-load-immediate

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1092

--- Comment #7 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Paul Mackerras from comment #3)
> Has thought been given about what fishmv should do in exception conditions?
> What if FRS contains a Signalling NaN initially? Should fishmv generate a
> VXSNAN exception in that case? Or do you consider this to be a move-type
> instruction (like fmr) which never generates exceptions?

this is a move-type instruction therefore never generates exceptions. this is
specifically necessary because otherwise fmvis/fishmv wouldn't be able to
encode all possible f32 sNaNs and end up with the exact same sNaN in the
register.

fmvis/fishmv is intended as a replacement for doing a f32 load from a constant,
so being able to express sNaNs is necessary

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