[Libre-soc-isa] [Bug 1056] questions and feedback (v2) on OPF RFC ls010

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sat Jun 17 01:03:43 BST 2023


--- Comment #74 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
Ah.  how about not adding a "Vector" Extension at all, just adding
a Prefix instruction:

SVPrefix  SV-Form

    |  0    5   | 6     29 | 30 31 |
    |   PO9     | SVRM     | svmode|

The SVPrefix instruction uses the following
Defined Word-instruction as a template for repetition in a loop.

The SVPrefix instruction suppresses or inhibits some debug
exceptions and inhibits interrupts on the following instruction

Hardware Engineering note: Implementations are possible from the
simplest Embedded Finite State Machine all the way to full Multi-Issue
Out-of-Order.  Multi-Issue systems should pay attention to
`SVSTATE.hphint` (reference-link) in order to greatly reduce hardware
complexity on Hazard Management. See section on SVSTATE SPR.

Special registers altered:


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