[Libre-soc-isa] [Bug 1056] questions and feedback (v2) on OPF RFC ls010

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1056

--- Comment #63 from Paul Mackerras <paulus at ozlabs.org> ---
(In reply to Luke Kenneth Casson Leighton from comment #54)
> 
> jacob and i went to a LOT of trouble to ensure that SV is an
> orthogonal consistent RISC paradigm.

Just as a side note, orthogonality does have an engineering cost, particularly
in terms of verification. Sometimes it is pragmatically necessary to limit
orthogonality in order to keep the verification state space manageable. In this
case, that might mean having a defined set of scalar instructions which can be
vectorized, rather than saying that almost any scalar instruction can be
vectorized. I know that seems sub-optimal conceptually, but it may be necessary
for practical reasons, particularly for an initial implementation. The set of
vectorizable instructions can always be expanded later.

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