[Libre-soc-isa] [Bug 1056] questions and feedback (v2) on OPF RFC ls010

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Tue Jun 6 02:08:56 BST 2023


--- Comment #62 from Paul Mackerras <paulus at ozlabs.org> ---
(In reply to Luke Kenneth Casson Leighton from comment #56)
> to that end can i suggest doing a trial-run on one single instruction?
> (i would recommend addi precisely because it is EXT1xx prefixable)
> edit: made a start
> https://libre-soc.org/openpower/sv/rfc/ls010/trial_addi/

This has a lot going for it. It doesn't express the looping aspect of sv.addi,
but that may well be preferable, i.e. we probably want to define the looping in
the SV chapter and say that the individual instruction descriptions just define
one iteration.

(I think you need to change 'if "addi" then' in the RTL to 'if "addi" or
"sv.addi" then'.)

On that page you say "a danger of even declaring the existence "sv.addi
RT,RA,SI" is the assumption that it is different from addi RT,RA,SI". People
don't get to make assumptions about what sv.addi is; you get to define it for
them. If people have latitude to make assumptions about it then the spec is not
precise enough.

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