[Libre-soc-isa] [Bug 1056] questions and feedback (v2) on OPF RFC ls010

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1056

--- Comment #55 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #51)
> (In reply to Paul Mackerras from comment #41)

> > element-width
> > overrides, saturation, etc., from the VF loop. Does that happen, or is it
> > the case that an addi without SVP64 prefix is never subject to any
> > modification (i.e. it only ever accesses the GPRs specified by RA and RT in
> > the instruction word)?
> 
> correct.

i just realised this example is not fully illustrative, let me add
some extra instructins ..

> https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/
> decoder/isa/test_caller_svp64_fft.py;h=fceb6b38#l612

 612             sv.fmuls 24, *0, *16       # mul1_r = r*cos_r
 613             sv.fmadds 24, *8, *20, 24  # mul2_r = i*sin_i

                 fadds 25,24,31  # here is definitely scalar
                 fmuls 25,25,30  # do as many as you like..
                 fsubs 24,24,31  # as long as fp24 is dest

 620             sv.ffadds *0, 24, *0       # vh/vl +/- tpre

the reason i added those extra instructions, they are definitely
scalar.  fp24 as a destination could become confused as being
"Vector" because it is used in an SVP64-prefix context, it isn't.

you can tell the difference by the "*" notation (from c pointer
notation)

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