[Libre-soc-isa] [Bug 1055] update ls004 OPF RFC to include LD-ST-Shifted instructions

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1055

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
btw jacob the strategy for this one - shift-and-add - is to include
*both* shift-and-add *and* the alternatives (the LD-ST-indexed-shifted
group) and let the OPF ISA WG evaluate which is better.

they might actually decide LD-ST-indexed-shifted is better, we just
never know.  given that both ARM and x86 have them, it's not actually
as hard a sell as it might sound even though it's 37 (!) instructions
(excluding ld-st-indexed-shifted-postincrement)

https://azeria-labs.com/memory-instructions-load-and-store-part-4/

-- 
You are receiving this mail because:
You are on the CC list for the bug.